What is metastability and what are its effect?
Whenever there is setup or hold time violations in a flip-flop, it enters a state where its output is unpredictable. This state of unpredictable output is known as metastable state.
To understand the cause metastability, one has to understand how a latch or a flop works. As shown in following figure a latch(or a flop) has an inverter feedback loop which acts as a memory element.
If you recall inverter voltage transfer curve, it look something like this.
For the inverter loop in the latch above, the voltage transfer curve gets superimposed and it can be seen in the figure below.
Wherever two curves are intersecting, those are the stable points for the inverter loop. You can see it has stability points along the X and Y axis. Those are the cases, input of the inverter loop is either at ‘0’ or Vmax voltage.
You can notice that there is one more point, where transfer curves intersect. This is when the input to the inverter loop is at Vmax/2 voltage. This is the metastable point along the curve. The loop can get stuck here for a very long period of time. But this point is not the most stable point for the inverters loop. The most stable points along the curve are the points along axis, when input is either ‘0’ or Vmax. Depending on the sizes of the inverters in the loop, eventually loop will converge to the most stable points.
When a value is to be written into the latch, the input value is driven through the input pin ‘D’ of the latch, while pass gate is open. This causes the latch node ‘I’ to be written ‘0’ or ‘1’ as input is strongly driven through pin ‘D’. Now if the pass gate is turned off earlier, while latch node ‘I’ has not completely reached to ‘0’ level or Vmax level, the node ‘I’ can get stuck near Vmax/2 value, which is a metastable point.
To avoid from this happening, the input has to be stable a certain time before the the pass gate closes. Pass gate closes when the clock arrives. As we’ll learn in other question, this is called the setup time for the latch.
Metastable state is also called quasi stable state. At the end of metastable state, the flip-flop settles down to either '1' or '0'. The whole process is known as metastability.
How to avoid metastability ?
If we ensure that input data meets setup and hold requirements, we can guarantee that we avoid metastability. Sometimes it’s not possible to guarantee to meet setup/hold requirements, especially generating signal is coming from a different clock domain compared to sampling clock.
In such cases, what we do is place back to back flip-flops and allocate extra timing cycles of clocks to sample the data. Such a series of back to back flops is called a metastability hardened flop.
As you can see in figure, input q to the first flop clocked by clkb changes right when clock is rising, by violating the setup time of this flop. This causes the flip-flop to go metastable, during first sampling clock cycle and we give first flop a full sampling clock cycle to recover from metastability. Within first cycle first flop recovers to correct value, we capture correct value at output second flip-flop at beginning of second clock cycle and qs is the correctly synchronized value available at the beginning of second clock cycle of clkb. If first flop recovers to wrong stage we’ve to wait for one more cycle i.e. beginning of 3rd cycle of sampling clock to capture the correct value.
Sometimes it’s possible that first flop takes longer than one sampling clock cycle to recover to stable value, in which case 3 flip-flops in series can be used. More flops in series reduces the failure in capturing the correct value at output at expense of more number of cycles.
How do you synchronize between 2 clock domains?
There are two ways to do this.
1) Asynchronous FIFO,
2) Synchronizer.
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